Silicon-on-insulator (SOI) structures for CMOS devices have been developed as an alternative to the bulk silicon device technology for very large scale integration (VLSI) circuits. The SOI structures are preferable because the use of the buried oxide insulator layer provides several advantages including the absence of the reverse body effect, absence of latch-up, soft error immunity and elimination of the parasitic junction capacitance typically encountered in bulk silicon devices. Reduction of the parasitic capacitance allows for greater circuit density, operation at higher circuit speeds, and reduced power consumption. FIG. 1 illustrates a typical SOI CMOS structure wherein buried oxide (BOX) layer 14, generally about 0.1-0.5 microns in thickness, is provided in the substrate 12, which comprises 400-600 microns of silicon. For the sake of illustration, substrate 12 is shown as a p-type silicon substrate, with an NMOSFET device formed at the surface. Clearly, the ensuing description of both the background and the novel structure and method will be applicable to devices formed in an n-type silicon substrate. The NMOSFET device, formed in the approximately 0.05 to 0.5 microns of crystalline silicon above the buried oxide layer, comprises polysilicon gate 15 and source and drain regions 16. Adjacent NMOSFET devices are both physically and electrically isolated from each other by shallow trench regions 17, comprised of an oxide region.
While SOI structures are advantageous for reduction of parasitic capacitance otherwise associated with bulk silicon CMOS devices, there are disadvantages to the isolation provided by the buried oxide layer. With the electrical isolation provided by the buried oxide, the devices cannot dissipate power or heat to the 400-600 micron silicon substrate, as efficiently as the bulk technology of the past had allowed. In bulk technology, the use of PN junction diodes, or NMOSFET devices with their gates grounded (operating in the so-called second breakdown regime) in parallel with diodes, provided electrostatic discharge (ESD) protection. ESD, primarily encountered through human contact or machine contact with the devices, and in shallow SOI structures gives rise to early failure of the devices, along with the possibilities of silicon melting, gate insulator rupture and metal melting due to the thermal build-up associated with the electrostatic discharge.
Solutions to the problem of ESD in bulk technology include the use of thick field oxide MOSFET's and large area PN diode junctions, neither of which is workable for SOI topographies. In an article entitled "ESD Reliability and Protection Schemes in SOI CMOS Output Buffers," published in IEEE Transactions on Electron Devices, Vol. 42, No. 10 (October 1995), pages 1816-1821, authors Mansun Chan, et al present and evaluate various ESD protection proposals for SOI structures. The article discussed the conventional grounded gate MOSFET built on the top superficial silicon layer, and optimization of such by alteration of gate-to-contact spacing, variation of the silicon film thickness, and adjustment of the effective channel width. With the foregoing modifications and optimizations, the device still does not provide the same level of protection as it would in bulk technology. The authors propose an alternative solution of providing a "through oxide buffer" for power dissipation.
The through oxide buffer ESD protection scheme of Chan, et al provides a path to contact the bulk substrate underlaying the buried oxide region, thereby emulating the power dissipation schemes used in bulk technology. FIG. 2 illustrates a device fabricated in accordance with the teachings of the Chan, et al article. The buried oxide layer 24 has been removed to allow ESD protection device formation in that area. One admitted shortcoming of the Chan, et al proposal is the height difference between the MOSFET and ESD protection device, which introduces problems in step coverage and residue removal during processing, and limits the device fabrication control for high performance circuits, given the limitations of current optical lithography tools (i.e., the depth of focus budget). Chan, et al specifically state that the proposed ESD protection scheme should not be considered for use for high performance circuits.
What is needed, therefore, is an ESD protection structure and method for fabrication of same which can be implemented for SOI technology without compromising the benefits of the SOI configuration.
It is therefore an objective of the present invention to provide an ESD protection structure for SOI devices.
It is additionally an objective of the invention to provide a method for creating ESD protection areas for SOI devices while maintaining a planar surface.
Yet another objective of the invention is to provide a method for incorporating ESD protection into SOI structures which is compatible with currently used SOI fabrication processes.